A non-volatile memory, such as a flash memory, is a semiconductor device, which retains its stored data even if it is powered off. Flash memory devices offer fast read access time and better shock resistance compared to hard disks. As a result, flash memory devices are popular in various applications, such as data storage on computing devices, mobile phones, portable audio players, and other consumer electronic products.
Some non-volatile memory devices operate in synchronism with an external clock provided by a memory controller. In such synchronous configuration, a data strobe signal may be used to indicate that data stored in a non-volatile memory device is available for access.
FIG. 1 shows a signal diagram 10 of a read operation for a non-volatile memory device. Signal diagram 10 illustrates a data strobe signal DQS synchronized to an external clock signal CLK for accessing a data signal DQ. A rising edge of the data strobe signal DQS is synchronized to a high logic level of the external clock signal CLK. A falling edge of the data strobe signal DQS is synchronized to a low logic level of the external clock signal CLK. Referring to the data strobe signal DQS and the data signal DQ, the first rising edge of the data strobe signal DQS indicates that a first bit (D0) of the data signal DQ is available for access. The first falling edge of the data strobe signal DQS indicates that a second bit (D1) of the data signal DQ is available for access.
Although a delay exists between the first rising edge of the data strobe signal DQS and the first rising edge of the external clock signal CLK, the data strobe signal DQS and the external clock signal CLK remain synchronized. That is, the data strobe signal DQS rises to a high logic level when the external clock signal CLK is at a high logic level. By synchronizing the data strobe signal DQS to the external clock signal CLK, the data signal DQ can be transferred with minimal error because the data strobe signal DQS, synchronized with the external clock CLK, appropriately indicates an availability of the data signal DQ.
However, as the speed or frequency of the external clock CLK continues to increase to achieve a higher rate of data transfer, the delay between the first rising edge of the data strobe signal DQS and the first rising edge of the external clock signal CLK becomes significant. FIG. 2 shows a signal diagram 20 of a data transfer of a read operation for a non-volatile memory device having an increased external clock speed. FIG. 2 denotes a first rising edge 22 of the external clock signal CLK, and first rising 24 and falling 26 edges of the data strobe signal DQS. A delay between first rising edge 24 of the data strobe signal DQS and first rising edge 22 of the external clock signal CLK is longer than the first high logic level of the external clock signal CLK. Because of the delay, first rising edge 24 of the data strobe signal DQS is no longer synchronized to the high logic level of the external clock signal CLK. For the same reason, falling edge 26 of the data strobe signal DQS is also not synchronized to a low logic level of the external clock signal CLK. Such delay may cause data transfer errors. The delay can be further exacerbated by unmatched loading/routing between DQ and DQS signal paths and/or simultaneous switching noise (caused by simultaneous switching of multiple buffers/inverters) on DQ or DQS signal lines. Additionally, the delay of the data strobe signal DQS relative to the external clock signal CLK may also be affected by various factors, such as operating temperature, operating voltage, and fabrication processes.